International Journal of Engineering Technology and Applied Science
ISSN (Online): 2395-3853
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Notice Board :
Call for Paper
Vol.
10
Issue
9
Submission Start Date:
September 1, 2024
Acceptence Notification Start:
September 20, 2024
Submission End:
September 26, 2024
Final ManuScript Due:
September 28, 2024
Publication Date:
September 30, 2024
Notice Board:
Call for PaperVol.
10
Issue
9
Submission Start Date:
September 1, 2024
Acceptence Notification Start:
September 20, 2024
Submission End:
September 26, 2024
Final ManuScript Due:
September 28, 2024
Publication Date:
September 30, 2024
Volume IV Issue III
Paper Title
Modelling and Simulation of Low Power ALU Using Pass Transistor Transmission Line Logic
Author Name
Priyanka Bharadwaj, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
Full Adder, which is the core of any arithmetic and logic unit that is the main component used in all the processors. This correspondence presents a design technique using pass transistor logic (PTL) and transmission gates for the architecture of full adder with minimum number of transistor and reduced delay.
PaperID
IJETAS/March/2018/08
Paper Title
Area Delay and Power Efficient 8-bit booth multiplier Design using pre encoded 4-bit radix of Design
Author Name
Pooja Jain, Prof.Dilip Ahirwar, Prof.Anupreksha Jain
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing thenumber of partial products. A multiplier using the radix-4 (or modified Booth)
PaperID
IJETAS/March/2018/13
Paper Title
Modelling and Simulation of Energy Efficient Spectrum Sensing Mechanism Using Hybrid Mechanism
Author Name
Swati Nema, Prof.Geetesh Wagadre, Prof. Jitendra Mishra
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
To identify the present or absent of licensed users, spectrum sensing techniques are used. Matched filter detection, Energy detection, and Cyclo-stationary feature detection are the three conventional methods used for spectrum sensing.
PaperID
IJETAS/March/2018/17
Paper Title
A CMOS Full Adder Design for low power applications Using Hybrid Logic
Author Name
Bhagyalaxmi Patsariya, Prof.Susmita Bilani, Prof.Dilip Ahirwar, Prof.R. S. Pandey
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
In this paperthearchitecture designsspeed andarea efficienttransistor base adder usingstaticCMOSpasstransistorlogic.Inthisworkthe longest critical path shortened to decreasethetotal criticalpath delay.
PaperID
IJETAS/March/2018/21
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