International Journal of Engineering Technology and Applied Science

ISSN (Online): 2395-3853






Notice Board :

Call for Paper
Vol. 11 Issue 4

Submission Start Date:
April 1, 2025

Acceptence Notification Start:
April 20, 2025

Submission End:
April 25, 2025

Final ManuScript Due:
April 29, 2025

Publication Date:
April 30, 2025
                         Notice Board: Call for PaperVol. 11 Issue 4      Submission Start Date: April 1, 2025      Acceptence Notification Start: April 20, 2025      Submission End: April 25, 2025      Final ManuScript Due: April 29, 2025      Publication Date: April 30, 2025



Volume IV Issue II

Paper Title
Designing and Simulation of High Speed Area Efficient Full Adder Using Pass Transistor Logic
Author Name
Ashutosh Kumar Yadav, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 2
Abstract
Full Adder is the heart of any central processing unit that is a core component employed in all the processors. This thesis presents a design methodology using pass transistor logic and transmission gates for the architecture of full adder with minimum number of transistor i.e.
PaperID
IJETAS/February/2018/03

Paper Title
A Literature Review on High Speed Area Efficient Using Different Energy Efficient Approaches
Author Name
Priyanka Bharadwaj, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 2
Abstract
In this paper, Authors have presented the literature on coming up with of high speed, less area 64-bit ALU using economical techniques. The optimization of the projected style can be done by using the various techniques. The parameters speed and area of the projected style can be improved by using Carry Look Ahead Techniques.
PaperID
IJETAS/February/2018/05