Notice Board :

Call for Paper
Vol. 12 Issue 1

Submission Start Date:
January 1, 2026

Acceptence Notification Start:
January 20, 2026

Submission End:
January 25, 2026

Final ManuScript Due:
January 29, 2026

Publication Date:
January 31, 2026
                         Notice Board: Call for PaperVol. 12 Issue 1      Submission Start Date: January 1, 2026      Acceptence Notification Start: January 20, 2026      Submission End: January 25, 2026      Final ManuScript Due: January 29, 2026      Publication Date: January 31, 2026



Volume III Issue XI

Author Name
Swadesh Dubey, Dilip Ahirwar, Susmita Bilani, R. S. Pandey
Year Of Publication
2017
Volume and Issue
Volume 3 Issue 11
Abstract
Full Adder is the heart of any central processing unit that is a core component employed in all the processors. This thesis presents a design methodology using pass transistor logic and transmission gates for the architecture of full adder with minimum number of transistor i.e.
PaperID
IJETAS/November/2017/07

Author Name
Sapna Singh , Dhirendra Mishra
Year Of Publication
2017
Volume and Issue
Volume 3 Issue 11
Abstract
In network security, cryptography has a long history by provides a way to store sensitive information or transmit it across insecure networks (i.e. the Internet) so that it cannot be read by anyone except the intended recipient
PaperID
IJETAS/November/2017/10

Author Name
Danish Wasim Khan, Prof. Mukesh Saini, Prof. Jitendra Mishra
Year Of Publication
2017
Volume and Issue
Volume 3 Issue 11
Abstract
a fusion-based distinction improvement technique that integrates information to beat the constraints of assorted distinction improvement algorithms.
PaperID
IJETAS/November/2017/09