International Journal of Engineering Technology and Applied Science
ISSN (Online): 2395-3853
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Notice Board :
Call for Paper
Vol.
12
Issue
4
Submission Start Date:
April 1, 2026
Acceptence Notification Start:
April 20, 2026
Submission End:
April 25, 2026
Final ManuScript Due:
April 28, 2026
Publication Date:
April 30 , 2026
Notice Board:
Call for PaperVol.
12
Issue
4
Submission Start Date:
April 1, 2026
Acceptence Notification Start:
April 20, 2026
Submission End:
April 25, 2026
Final ManuScript Due:
April 28, 2026
Publication Date:
April 30 , 2026
Volume V Issue II
Paper Title
Modelling and Simulation of Low Power ALU Using Hybrid Pass Transistor Transmission Line Logic
Author Name
Mr.Vinod, Prof.Ashish Raghuwanshi
Year Of Publication
2019
Volume and Issue
Volume 5 Issue 2
Abstract
Full Adder, which is the core of any arithmetic and logic unit that is the main component used in all the processors. T
PaperID
IJETAS/February/2019/04
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