International Journal of Engineering Technology and Applied Science

ISSN (Online): 2395-3853






Notice Board :

Call for Paper
Vol. 11 Issue 7

Submission Start Date:
July 1, 2025

Acceptence Notification Start:
July 20, 2025

Submission End:
July 25, 2025

Final ManuScript Due:
July 29, 2025

Publication Date:
July 31, 2025
                         Notice Board: Call for PaperVol. 11 Issue 7      Submission Start Date: July 1, 2025      Acceptence Notification Start: July 20, 2025      Submission End: July 25, 2025      Final ManuScript Due: July 29, 2025      Publication Date: July 31, 2025



Volume V Issue II

Paper Title
Modelling and Simulation of Low Power ALU Using Hybrid Pass Transistor Transmission Line Logic
Author Name
Mr.Vinod, Prof.Ashish Raghuwanshi
Year Of Publication
2019
Volume and Issue
Volume 5 Issue 2
Abstract
Full Adder, which is the core of any arithmetic and logic unit that is the main component used in all the processors. T
PaperID
IJETAS/February/2019/04