International Journal of Engineering Technology and Applied Science
ISSN (Online): 2395-3853
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Notice Board :
Call for Paper
Vol.
10
Issue
11
Submission Start Date:
November 1, 2024
Acceptence Notification Start:
November 20, 2024
Submission End:
November 26, 2024
Final ManuScript Due:
November 28, 2024
Publication Date:
November 30, 2024
Notice Board:
Call for PaperVol.
10
Issue
11
Submission Start Date:
November 1, 2024
Acceptence Notification Start:
November 20, 2024
Submission End:
November 26, 2024
Final ManuScript Due:
November 28, 2024
Publication Date:
November 30, 2024
Volume V Issue II
Paper Title
Modelling and Simulation of Low Power ALU Using Hybrid Pass Transistor Transmission Line Logic
Author Name
Mr.Vinod, Prof.Ashish Raghuwanshi
Year Of Publication
2019
Volume and Issue
Volume 5 Issue 2
Abstract
Full Adder, which is the core of any arithmetic and logic unit that is the main component used in all the processors. T
PaperID
IJETAS/February/2019/04
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